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PRELIMINARY
82093AA I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)
Provides Multiprocessor Interrupt Management Dynamic Interrupt DistributionRouting Interrupt to the Lowest Priority Processor Software Programmable Control of Interrupt Inputs Off Loads Interrupt Related Traffic From the Memory Bus 24 Programmable Interrupts 13 ISA Interrupts Supported 4 PCI Interrupts 1 Interrupt/SMI# Rerouting 2 Motherboard Interrupts 1 Interrupt Used for INTR Input
3 General Purpose Interrupts Independently Programmable for
Edge/Level Sensitivity Interrupts
Each Interrupt Can Be Programmed
to Respond to Active High or Low Inputs X-Bus Interface CS For Flexible Decode of the IOAPIC Device. Index Register Interface for Optimum Memory Usage Registers are 32-Bit Wide to Match the PCI to Host Bridge Architecture Package 64-Pin PQFP
The 82093AA I/O Advanced Programmable Interrupt Controller (IOAPIC) provides multi-processor interrupt management and incorporates both static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts. Each interrupt pin is individually programmable as either edge or level triggered. The interrupt vector and interrupt steering information can be specified per interrupt. An indirect register accessing scheme optimizes the memory space needed to access the IOAPIC's internal registers. To increase system flexibility when assigning memory space usage, the The IOAPIC's 2-register memory space is re-locatable.
D[7:0] D/I# A[1:0] RD# WR# CS# APCIREQ# APICACK1# APICACK2#
System Bus Interface
APIC Bus Interface
APCID[1:0] APCICLK
Interrupt Controller
APCID[1:0] APCICLK APCICLK
RESET CLK
Clock And Reset
Test
TESTIN#
IOA_BLK
Figure 1. IOAPIC Simplified Block Diagram
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by the sale of Intel products. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The 82093AA IOAPIC may contain design defects or errors known as errata. Current characterized errata are available on request. Third-party brands and names are the property of their respective owners.
(c) INTEL CORPORATION 1996
May 1996
Order Number: 290566-001
82093AA (IOAPIC)
CONTENTS
PAGE 1.0. OVERVIEW ......................................................................................................................................................3 2.0. SIGNAL DESCRIPTION ..................................................................................................................................5 2.1. System Bus Signals......................................................................................................................................5 2.2. Clock and Reset Signals...............................................................................................................................6 2.3. APIC Bus Interface .......................................................................................................................................6 2.4. Interrupt Signals ............................................................................................................................................6 2.5. Test and Power Signals ................................................................................................................................7 3.0. REGISTER DESCRIPTION .............................................................................................................................8 3.1. Memory Mapped Registers for Accessing IOAPIC Registers......................................................................9 3.1.1. IOREGSEL--I/O REGISTER SELECT REGISTER .............................................................................9 3.1.2. IOWIN--I/O WINDOW REGISTER.......................................................................................................9 3.2. IOAPIC Registers .........................................................................................................................................9 3.2.1. IOAPICID--IOAPIC IDENTIFICATION REGISTER .............................................................................9 3.2.2. IOAPICVER--IOAPIC VERSION REGISTER....................................................................................10 3.2.3. IOAPICARB--IOAPIC ARBITRATION REGISTER............................................................................10 3.2.4. IOREDTBL[23:0]--I/O REDIRECTION TABLE REGISTERS ............................................................11 4.0. FUNCTIONAL DESCRIPTION ......................................................................................................................14 4.1. INTIN23/SMI# and SMIOUT# Functionality................................................................................................14 5.0. PINOUT AND PACKAGE SPECIFICATIONS ..............................................................................................15 5.1. Pinout Specifications...................................................................................................................................15 5.2. Package Specifications...............................................................................................................................17 6.0. TESTABILITY.................................................................................................................................................18 6.1. Tri-State Of All Output Pins.........................................................................................................................18 6.2. Drive 1's to all the output pins.....................................................................................................................18 6.3. Drive 0's to all the output pins.....................................................................................................................19 6.4. NAND Tree .................................................................................................................................................19
2
PRELIMINARY
82093AA (IOAPIC)
1.0.
OVERVIEW
While the standard ISA Compatible interrupt controller (located in the PIIX3) is intended for use in a uniprocessor system, the I/O Advanced Programmable Interrupt Controller (IOAPIC) can be used in either a uniprocessor or multi-processor system. The IOAPIC provides multi-processor interrupt management and incorporates both static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts. In a uni-processor system, the IOAPIC's dedicated interrupt bus can reduce interrupt latency over the standard interrupt controller (i.e., the latency associated with the propagation of the interrupt acknowledge cycle across multiple busses using the standard interrupt controller approach). Interrupts can be controlled by the standard ISA Compatible interrupt controller in the PIIX3, the IOAPIC unit, or mixed mode where both the standard ISA Compatible Interrupt Controller and IOAPIC are used. The selection of which controller responds to an interrupt is determined by how the interrupt controllers are programmed. Note that it is the programmer's responsibility to make sure that the same interrupt input signal is not handled by both interrupt controllers. At the system level, APIC consists of two parts (Figure 2.0)--one residing in the I/O subsystem (called the IOAPIC) and the other in the CPU (called the Local APIC). The local APIC and the IOAPIC communicate over a dedicated APIC bus. The IOAPIC bus interface consists of two bi-directional data signals (APICD[1:0]) and a clock input (APICCLK). The CPU's Local APIC Unit contains the necessary intelligence to determine whether or not its processor should accept interrupts broadcast on the APIC bus. The Local Unit also provides local pending of interrupts, nesting and masking of interrupts, and handles all interactions with its local processor (e.g., the INTR/INTA/EOI protocol). The Local Unit further provides inter-processor interrupts and a timer, to its local processor. The register level interface of a processor to its local APIC is identical for every processor. The IOAPIC Unit consists of a set of interrupt input signals, a 24-entry by 64-bit Interrupt Redirection Table, programmable registers, and a message unit for sending and receiving APIC messages over the APIC bus. I/O devices inject interrupts into the system by asserting one of the interrupt lines to the IOAPIC. The IOAPIC selects the corresponding entry in the Redirection Table and uses the information in that entry to format an interrupt request message. Each entry in the Redirection Table can be individually programmed to indicate edge/level sensitive interrupt signals, the interrupt vector and priority, the destination processor, and how the processor is selected (statically or dynamically). The information in the table is used to transmit a message to other APIC units (via the APIC bus). The IOAPIC contains a set of programmable registers. Two of the registers (I/O Register Select and I/O Window Registers) are located in the CPU's memory space and are used to indirectly access the other APIC registers as described in Section 3.0, Register Description. The Version Register provides the implementation version of the IOAPIC. The IOAPIC ID Register is programmed with an ID value that serves as a physical name of the IOAPIC. This ID is loaded into the ARB ID Register when the IOAPIC ID Register is written and is used during bus arbitration. NOTE The interrupt number or the vector does not imply a particular priority for being sent. The IOAPIC continually polls the 24 interrupts in a rotating fashion, one at a time. The pending interrupt polled first is the one sent.
PRELIMINARY
3
82093AA (IOAPIC)
Processor
Processor
Local APIC
NMI LINTIN1 LINTIN0 LINTIN0 LINTIN1 SMI#
RESET
RESET LINTIN0
Local APIC
LINTIN1 SMI#
SMI RESET Host-to-PCI Bridge APICACK2# RESET SMIOUT# APIC Bus
PCI Bus
CS# APICREQ# APICACK1# PIIX3 INTIN23/SMI# INTR MIRQ[1:0] IRQ[1,2:7,8#,9:12,14,15]
I/O APIC Unit
INTIN[2,13,22] MIRQ[1:0]
ISA Bus
APIC_SYS
Figure 2. I/O And Local APIC Units
4
PRELIMINARY
82093AA (IOAPIC)
2.0.
SIGNAL DESCRIPTION
This section contains a detailed description of each signal. The signals are arranged in function groups according to their interface. Note that the "#" symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "#" is not present after the signal name, the signal is asserted when at the high voltage level. The terms' assertion and negation are used extensively. This is done to avoid confusion when working with a mixture of `active-low' and `active-high' signals. The term assert, or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation indicates that a signal is inactive. The following notations are used to describe the signal and type: I O ST OD I/OD I/O Input pin Output pin Schmitt Trigger Input pin Open Drain Output pin. This requires a pull-up to the VCC of the processor core Bi-directional Input withOpen Drain Output pin. Bi-directional Input/Output pin
2.1.
D[7:0]
System Bus Signals
Type I/O Description DATA: D[7:0] contain the data when writing to or reading from internal IOAPIC registers. These signals are outputs when reading data from the IOAPIC and they are inputs when writing data to the IOAPIC. These signals are tri-stated during reset. DATA/INDEX#: This input selects whether the I/O Register Select (IOREGSEL) Register or I/O Window (IOWIN) Register is accessed. All internal IOAPIC registers are accessed with an indexing scheme. When the D/I# pin is low, the IOREGSEL Register is accessed. When the D/I# pin is high, the data becomes available from the register pointed to by the index register. Typically, this signal is connected to SA4 on the ISA bus (i.e., IOREGSEL Register is at 00h and IOWIN Register is at 10h). ADDRESS: The IOAPIC is a 32 bit device with an 8 bit ISA interface. A[1:0] steer the data byte to the correct 8 bit location within the 32 bit register. Typically, these input signals are connected to SA[1:0] of the ISA bus. READ STROBE: RD# causes the IOAPIC to respond by driving internal register data onto the D[7:0] pins. Typically this pin is connected to the MEMRD# signal on the ISA bus. WRITE STROBE: When this signal transitions from low to high, the data present on the IOAPIC's D[7:0] signals are written to an internal register. Typically, this signal is connected to the MEMWR# signal on the ISA bus. CHIP SELECT: This active low input selects the IOAPIC as the target of the current read or write transaction.
Signal Name
D/I#
I
A[1:0]
I
RD#
I
WR#
I
CS#
I
PRELIMINARY
5
82093AA (IOAPIC)
Signal Name APICREQ#
Type O
Description APIC REQUEST: APICREQ# is asserted prior to the APIC sending an interrupt message over the APIC data bus. This is the request part of a handshake that insures system level buffer coherency prior to sending an interrupt over the APIC bus. This signal is tri-stated during reset. This signal has an internal pull-up resistor. APIC ACKNOWLEDGE 1: This signal is the acknowledge part of the handshake indicating that the APIC can send the interrupt message over the APIC bus. This signal is typically connected to the PIIX3. APIC ACKNOWLEDGE 2: This signal is the second half of the acknowledge handshake indicating that the APIC can send the interrupt message over the APIC bus. This signal is typically connected to the host-to-PCI bridge and along with APICREQ# and APICACK1# makes up the complete buffer coherency protocol cycles. If the system does not have a host-to-PCI bridge, this signal can be tied low.
APICACK1#
I
APICACK2#
I
2.2.
Clock and Reset Signals
Type I Description PCI CLOCK: This signal is used to synchronize and strobe the data buffer status signals (APICREQ#, APICACK1#, and APICACK2#). This signal is typically connect to the PCI clock. RESET: RESET initializes the IOAPIC's internal logic and sets the register bits to their default value.
Signal Name PCICLK
RESET
I
2.3.
APIC Bus Interface
Type I/OD Description APIC DATA: These signals are used to send and receive data over the APIC bus. These signals are tri-stated during reset and must be pulled up to the appropriate VCC levels of the CPU. APIC CLOCK: The input signal is used to determine when valid data is being sent over the APIC bus.
Signal Name APICD[1:0]
APICCLK
I
2.4.
INTIN0
Interrupt Signals
Type ST Description Interrupt Input 0: This signal is connected to the redirection table entry 0. Typically, this signal may be connected to the INTR on the PIIX3 to communicate the status of IRQ0 and IRQ13 interrupts. Note that the IRQ0 and IRQ13 interrupts are embedded in the PIIX3 and are not available to the rest of the system. Interrupt Input 1: INTIN1 is connected to the redirection table entry 1. Typically, this signal will be connected to the keyboard interrupt (IRQ1).
Signal Name
INTIN1
ST
6
PRELIMINARY
82093AA (IOAPIC)
Signal Name INTIN2 INTIN[3:11, 14,15] INTIN12 INTIN13
Type ST ST
Description Interrupt Input 2: This signal is connected to the redirection table entry 2. If IRQ0 interrupt is available in hardware, it is connected to this pin. Interrupt Inputs 3 through 11, 14 and 15: These signals are connected to the redirection table entries 3:11, 14 & 15. Typically, these signals are connected to the ISA interrupts IRQ[3:7,8#,9:11,14:15] respectively. Interrupt Input 12: This signal is connected to the redirection table entry 12. Typically, this signal will be connected to the mouse interrupt (IRQ12/M). Interrupt input 13: This signal is connected to the redirection table entry 13. If IRQ13 interrupt is available in hardware, it is connected to this signal. If IRQ13 is not available, it is routed through the INTR interrupt and this signal becomes INTIN13 (redirection table entry 13). Interrupt inputs 16 through 19: These signals are connected to the redirection table entries [16:19]. Typically, these signals are connected to the PCI interrupts (PIRQ[0:3]). The steering of the PCI IRQs to the ISA IRQs is accomplished in the IOAPIC by setting the PCI redirection table entry to the correct ISA interrupt vector. Interrupt inputs 20 and 21: These signals are connected to the redirection table entries 20 and 21. Typically, these signals are connected to the motherboard interrupts (MIRQ[0:1]). These pins could be used for the NMI and INIT signals or just general purpose interrupts. Interrupt input 22: This signal is connect to the redirection table entry 22. This signal is a general purpose interrupt. Interrupt input 23: This signal is connected to the redirection table entry 23. This input has a special feature for the SMI# interrupt routing. If the Mask bit is not set, the signal is a normal interrupt input that is sent over the APIC bus just like all the other interrupts. When the Mask bit is set, the INTIN23/SMI# input is routed through the IOAPIC to the SMIOUT# output signal. SMI OUTPUT: This signal is an output in response to the SMI# input when the MASK bit for the redirection table entry number 23 is set. If the MASK bit is not set, the redirection table can be setup to deliver an SMI# over the APIC bus.
ST ST
INTIN[16:19]
ST
INTIN[20:21]
ST
INTIN22 INTIN23/ SMI#
ST ST
SMIOUT#
OD
2.5.
Test and Power Signals
Type I Description TEST INPUT: This active-low input is used to invoke test modes. TESTIN# should be pulled high during normal operation. VCC POWER PIN: 5V 10%. GROUND POWER PIN:
Pin Name TESTIN# VCC GND
PRELIMINARY
7
82093AA (IOAPIC)
3.0.
REGISTER DESCRIPTION
The IOAPIC is addressed with a CS# and the D/I# pin. The PIIX3 decodes the IOAPIC in memory space and sends a CS# to the IOAPIC device, when it is selected. The D/I# pin selects between the IOREGSEL Register (D/I#=0) and the IOWIN Register (D/I#=1). Typically, D/I# is connected to SA4 on the ISA bus (i.e., IOREGSEL Register is at 00h and IOWIN Register is at 10h). The IOAPIC registers are accessed by an indirect addressing scheme using two registers (IOREGSEL and IOWIN) that are located in the CPU's memory space (memory address specified by the APICBASE Register located in the PIIX3). These two registers are re-locateable (via the APICBASE Register) as shown in Table 3.1. In the IOAPIC only the IOREGSEL and IOWIN Registers are directly accesable in the memory address space. To reference an IOAPIC register, a byte memory write that the PIIX3 decodes for the IOAPIC loads the IOREGSEL Register with an 8-bit value that specifies the IOAPIC register (address offset in Table 3.2) to be accessed. The IOWIN Register is then used to read/write the desired data from/to the IOAPIC register specified by bits [7:0] of the IOREGSEL Register. The IOWIN Register must be accessed as a Dword quantity. The IOREGSEL and IOWIN Registers (Table 3.1) can be relocated via the APIC Base Address Relocation Register in the PIIX3 and are aligned on 128 bit boundaries. All APIC registers are accessed using 32 bit loads and stores. This implies that to modify a field (e.g., bit, byte) in any register, the whole 32 bit register must be read, the field modified, and the 32 bits written back. In addition, registers that are described as 64 bits wide are accessed as multiple independent 32 bit registers. Table 1. Memory Mapped Registers For Accessing IOAPIC Registers Memory Address FEC0 xy00h FEC0 xy10h Mnemonic IOREGSEL IOWIN Register Name I/O Register Select (index) I/O Window (data) Access R/W R/W D/I# SIgnal 0 1
NOTES: xy are determined by the x and y fields in the APIC Base Address Relocation Register located in the PIIX3. Range for x = 0-Fh and the range for y = 0,4,8,Ch.
Table 2. IOAPIC Registers Address Offset 00h 01h 02h 10-3Fh Mnemonic IOAPICID IOAPICVER IOAPICARB IOREDTBL[0:23] IOAPIC ID IOAPIC Version IOAPIC Arbitration ID Redirection Table (Entries 0-23) (64 bits each) Register Name Access R/W RO RO R/W
NOTES: Address Offset is determined by I/O Register Select Bits [7:0].
8
PRELIMINARY
82093AA (IOAPIC)
3.1.
3.1.1.
Memory Mapped Registers for Accessing IOAPIC Registers
IOREGSEL--I/O REGISTER SELECT REGISTER FEC0 xy00h (xy=See APICBASE Register in the PIIX3) 00h Read/Write
Memory Address: Default Value: Attribute:
This register selects the IOAPIC Register to be read/written. The data is then read from or written to the selected register through the IOWIN Register. Bit 31:8 7:0 Reserved. APIC Register Address--R/W. Bits [7:0] specify the IOAPIC register to be read/written via the IOWIN Register. Description
3.1.2.
IOWIN--I/O WINDOW REGISTER FEC0 xy10h (xy=See APICBASE Register in PIIX3) 00h Read/Write
Memory Address: Default Value: Attribute:
This register is used to write to and read from the register selected by the IOREGSEL Register. Readability/writability is determined by the IOAPIC register that is currently selected. Bit 31:0 Description APIC Register Data--R/W. Memory references to this register are mapped to the APIC register specified by the contents of the IOREGSEL Register.
3.2.
3.2.1.
IOAPIC Registers
IOAPICID--IOAPIC IDENTIFICATION REGISTER 00h 00h Read/Write
Address Offset: Default Value: Attribute:
This register contains the 4-bit APIC ID. The ID serves as a physical name of the IOAPIC. All APIC devices using the APIC bus should have a unique APIC ID. The APIC bus arbitration ID for the I/O unit is also writtten during a write to the APICID Register (same data is loaded into both). This register must be programmed with the correct ID value before using the IOAPIC for message transmission. Bit 31:28 27:24 23:0 Reserved. IOAPIC Identification--R/W. This 4 bit field contains the IOAPIC identification. Reserved. 9 Description
PRELIMINARY
82093AA (IOAPIC)
3.2.2. IOAPICVER--IOAPIC VERSION REGISTER 01h 00170011h Read Only
Address Offset: Default Value: Attribute:
The IOAPIC Version Register identifies the APIC hardware version. Software can use this to provide compatibility between different APIC implementations and their versions. In addition, this register provides the maximum number of entries in the I/O Redirection Table. Bit 31:24 23:16 Reserved. Maximum Redirection Entry--RO. This field contains the entry number (0 being the lowest entry) of the highest entry in the I/O Redirection Table. The value is equal to the number of interrupt input pins for the IOAPIC minus one. The range of values is 0 through 239. For this IOAPIC, the value is 17h. Reserved. APIC VERSION--RO. This 8 bit field identifies the implementation version. The version number assigned to the IOAPIC is 11h. Descriptions
15:8 7:0
3.2.3.
IOAPICARB--IOAPIC ARBITRATION REGISTER 02h 0000_0000h Read Only
Address Offset: Default Value: Attribute:
The APICARB Register contains the bus arbitration priority for the IOAPIC. This register is loaded when the IOAPIC ID Register is written. The APIC uses a one wire arbitration to win bus ownership. A rotating priority scheme is used for arbitration. The winner of the arbitration becomes the lowest priority agent and assumes an arbitration ID of 0. All other agents, except the agent whose arbitration ID is 15, increment their arbitration IDs by one. The agent whose ID was 15 takes the winner's arbitration ID and increments it by one. Arbitration IDs are changed (incremented or asssumed) only for messages that are transmitted successfully (except, in the case of low priority messages where Arbitration ID is changed even if message was not successfully transmitted). A message is transmitted successfully if no checksum error or acceptance error is reported for that message. The APICARB Register is always loaded with IOAPIC ID during a "level triggered INIT with de-assert" message. Bit 31:28 27:24 23:0 Reserved. IOAPIC Identification--R/W. This 4 bit field contains the IOAPIC Arbitration ID. Reserved. Description
10
PRELIMINARY
82093AA (IOAPIC)
3.2.4. IOREDTBL[23:0]--I/O REDIRECTION TABLE REGISTERS 10-11h (IOREDTBL0) 12-13h (IOREDTBL1) 14-15h (IOREDTBL2) 16-17h (IOREDTBL3) 18-19h (IOREDTBL4) 1A-1Bh (IOREDTBL5) 1C-1Dh (IOREDTBL6) 1E-1Fh (IOREDTBL7) 20-21h (IOREDTBL8) 22-23h (IOREDTBL9) 24-25h (IOREDTBL10) 26-27h (IOREDTBL11) xxx1 xxxx xxxx xxxxh Read/Write 28-29h (IOREDTBL12) 2A-2Bh (IOREDTBL13) 2C-2Dh (IOREDTBL14) 2E-2Fh (IOREDTBL15) 30-31h (IOREDTBL16) 32-33Fh (IOREDTBL17) 34-35h (IOREDTBL18) 36-37h (IOREDTBL19) 38-39h (IOREDTBL20) 3A-3Bh (IOREDTBL21) 3C-3Dh (IOREDTBL22) 3E-3Fh (IOREDTBL23)
Address Offset:
Default Value: Attribute:
There are 24 I/O Redirection Table entry registers. Each register is a dedicated entry for each interrupt input signal. Unlike IRQ pins of the 8259A, the notion of interrupt priority is completely unrelated to the position of the physical interrupt input signal on the APIC. Instead, software determines the vector (and therefore the priority) for each corresponding interrupt input signal. For each interrupt signal, the operating system can also specify the signal polarity (low active or high active), whether the interrupt is signaled as edges or levels, as well as the destination and delivery mode of the interrupt. The information in the redirection table is used to translate the corresponding interrupt pin information into an inter-APIC message. The IOAPIC responds to an edge triggered interrupt as long as the interrupt is wider than one CLK cycle. The interrupt input is asynchronous; thus, setup and hold times need to be guaranteed for at lease one rising edge of the CLK input. Once the interrupt is detected, a delivery status bit internal to the IOAPIC is set. A new edge on that Interrupt input pin will not be recongnized until the IOAPIC Unit broadcasts the corresponding message over the APIC bus and the message has been accepted by the destination(s) specified in the destination field. That new edge only results in a new invocation of the handler if its acceptance by the destination APIC causes the Interrupt Request Register bit to go from 0 to 1. (In other words, if the interrupt wasn't already pending at the destination.) Bit 63:56 Description Destination Field--R/W. If the Destination Mode of this entry is Physical Mode (bit 11=0), bits [59:56] contain an APIC ID. If Logical Mode is selected (bit 11=1), the Destination Field potentially defines a set of processors. Bits [63:56] of the Destination Field specify the logical destination address. Destination Mode IOREDTBLx[11] 0, Physical Mode 1, Logical Mode 55:17 Reserved. Logical Destination Address IOREDTBLx[59:56] = APIC ID IOREDTBLx[63:56] = Set of processors
PRELIMINARY
11
82093AA (IOAPIC)
Bit 16
Description Interrupt Mask--R/W. When this bit is 1, the interrupt signal is masked. Edge-sensitive interrupts signaled on a masked interrupt pin are ignored (i.e., not delivered or held pending). Level-asserts or negates occurring on a masked level-sensitive pin are also ignored and have no side effects. Changing the mask bit from unmasked to masked after the interrupt is accepted by a local APIC has no effect on that interrupt. This behavior is identical to the case where the device withdraws the interrupt before that interrupt is posted to the processor. It is software's responsibility to handle the case where the mask bit is set after the interrupt message has been accepted by a local APIC unit but before the interrupt is dispensed to the processor. When this bit is 0, the interrupt is not masked. An edge or level on an interrupt pin that is not masked results in the delivery of the interrupt to the destination. Trigger Mode--R/W. The trigger mode field indicates the type of signal on the interrupt pin that triggers an interrupt. 1=Level sensitive, 0=Edge sensitive. Remote IRR--RO. This bit is used for level triggered interrupts. Its meaning is undefined for edge triggered interrupts. For level triggered interrupts, this bit is set to 1 when local APIC(s) accept the level interrupt sent by the IOAPIC. The Remote IRR bit is set to 0 when an EOI message with a matching interrupt vector is received from a local APIC. Interrupt Input Pin Polarity (INTPOL)--R/W. This bit specifies the polarity of the interrupt signal. 0=High active, 1=Low active. Delivery Status (DELIVS)--RO. The Delivery Status bit contains the current status of the delivery of this interrupt. Delivery Status is read-only and writes to this bit (as part of a 32 bit word) do not effect this bit. 0=IDLE (there is currently no activity for this interrupt). 1=Send Pending (the interrupt has been injected but its delivery is temporarily held up due to the APIC bus being busy or the inability of the receiving APIC unit to accept that interrupt at that time). Destination Mode (DESTMOD)--R/W. This field determines the interpretation of the Destination field. When DESTMOD=0 (physical mode), a destination APIC is identified by its ID. Bits 56 through 59 of the Destination field specify the 4 bit APIC ID. When DESTMOD=1 (logical mode), destinations are identified by matching on the logical destination under the control of the Destination Format Register and Logical Destination Register in each Local APIC. Destination Mode IOREDTBLx[11] 0, Physical Mode 1, Logical Mode Logical Destination Address IOREDTBLx[59:56] = APIC ID IOREDTBLx[63:56] = Set of processors
15 14
13 12
11
12
PRELIMINARY
82093AA (IOAPIC)
Bit 10:8
Description Delivery Mode (DELMOD)--R/W. The Delivery Mode is a 3 bit field that specifies how the APICs listed in the destination field should act upon reception of this signal. Note that certain Delivery Modes only operate as intended when used in conjunction with a specific trigger Mode. These restrictions are indicated in the following table for each Delivery Mode. Bits [10:8] Mode 000 001 Fixed Lowest Priority Deliver the signal on the INTR signal of the processor core that is executing at the lowest priority among all the processors listed in the specified destination. Trigger Mode for "lowest priority". Delivery Mode can be edge or level. System Management Interrupt. A delivery mode equal to SMI requires an edge trigger mode. The vector information is ignored but must be programmed to all zeroes for future compatibility. Description Deliver the signal on the INTR signal of all processor cores listed in the destination. Trigger Mode for "fixed" Delivery Mode can be edge or level.
010
SMI
011 100
Reserved NMI Deliver the signal on the NMI signal of all processor cores listed in the destination. Vector information is ignored. NMI is treated as an edge triggered interrupt, even if it is programmed as a level triggered interrupt. For proper operation, this redirection table entry must be programmed to "edge" triggered interrupt. Deliver the signal to all processor cores listed in the destination by asserting the INIT signal. All addressed local APICs will assume their INIT state. INIT is always treated as an edge triggered interrupt, even if programmed otherwise. For proper operation, this redirection table entry must be programmed to "edge" triggered interrupt.
101
INIT
110 111
Reserved ExtINT Deliver the signal to the INTR signal of all processor cores listed in the destination as an interrupt that originated in an externally connected (8259A-compatible) interrupt controller. The INTA cycle that corresponds to this ExtINT delivery is routed to the external controller that is expected to supply the vector. A Delivery Mode of "ExtINT" requires an edge trigger mode.
7:0
Interrupt Vector (INTVEC)--R/W: The vector field is an 8 bit field containing the interrupt vector for this interrupt. Vector values range from 10h to FEh.
PRELIMINARY
13
82093AA (IOAPIC)
4.0. 4.1.
FUNCTIONAL DESCRIPTION INTIN23/SMI# and SMIOUT# Functionality
The SMI# interrupt pin can be routed through the IOAPIC device. The redirection table entry can be programmed to send an SMI# interrupt over the APIC bus. The SMI# input is sent over the APIC bus when the delivery mode register is set to 010 for INTIN23/SMI# input and the Mask bit is set to 0. During this time, the SMIOUT# pin is inactive. If the Mask bit is set to 1, the INTIN23/SMI# input is routed to the SMIOUT# pin on the IOAPIC. Refer to Figure 3. If the SMI# routing feature is not desired, the SMIOUT# pin is not connected to SMI# of the CPU's. The SMIOUT# pin is left open in the system. The INTIN23/SMI# redirection table entry has the same functionality as all other redirection table entries.
31
17
16 Mask
15
14
13
12
11
10 Delivery 010=SMI
8
7 Vector
0
Mask Bit 0=APIC Bus 1=SMIOUT# INTIN23/SMI# SMIOUT#
APIC_IR
Figure 3. INTIN23/SMI# Routing And Control From Redirection Table Mask Bit
14
PRELIMINARY
82093AA (IOAPIC)
5.0. 5.1.
PINOUT AND PACKAGE SPECIFICATIONS Pinout Specifications
GND PCICLK TESTIN# APICDO APICD1 SMIOUT# NC APICACK2# APICREQ# APICACK1# WR# RD# A0 A1 D/I# INTIN13 INTIN0 INTIN14 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
82093AA
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VCC D7 NC NC NC NC NC INTIN23/SMI# INTIN22 INTIN21 INTIN20 INTIN19 INTIN18 INTIN17 INTIN16 NC INTIN2 INTIN1 GND
IOA_PIN
Figure 4. IOAPIC Pinout
PRELIMINARY
15
82093AA (IOAPIC)
Table 3. Alphabetical Pinout List Name A0 A1 APICACK1# APICACK2# APICCLK APICD0 APICD1 APICREQ# CS# D/I# D0 D1 D2 D3 D4 D5 D6 D7 GND GND GND INTIN0 Pin 13 14 10 8 62 4 5 9 61 15 59 58 57 56 55 54 53 50 1 33 52 17 I I I I I I/OD I/OD O I I I/O I/O I/O I/O I/O I/O I/O I/O V V V ST Type
Table 3. Alphabetical Pinout List Name INTIN1 INTIN10 INTIN11 INTIN12 INTIN13 INTIN14 INTIN15 INTIN16 INTIN17 INTIN18 INTIN19 INTIN2 INTIN20 INTIN21 INTIN22 Pin 34 24 23 22 16 18 21 37 38 39 40 35 41 42 43 Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST
Table 3. Alphabetical Pinout List Name INTIN9 NC NC NC NC NC NC NC NC NC NC PCICLK RD# RESET SMIOUT# TESTIN# VCC VCC VCC WR# Pin 30 7 20 32 36 45 46 47 48 49 63 2 12 60 6 3 19 51 64 11 Type ST I I I OD I V V V I
INTIN23/SMI# 44 INTIN3 INTIN4 INTIN5 INTIN6 INTIN7 INTIN8 25 26 27 28 29 31
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PRELIMINARY
82093AA (IOAPIC)
5.2.
Package Specifications
D D1 A1
1 L1 e1
E1
E
A
Y
b
Units: mm
ioa_pkg
Figure 5. IOAPIC 64-Pin Quad Flat Pack (QFP) Table 4. IOAPIC 64-Pin Quad Flat Pack (QFP) Symbol Description Min. A A1 b D D1 E E1 e1 Y L1 Seating Height Stand-off Lead Width Package Width, including pins Package Width, excluding pins Package Length, including pins Package Length, excluding pins Linear Lead Pitch Lead Coplanarity Foot Length 0.65 (0.026) 0.35 (0.014) 17.65 (0.695) 13.90 (0.547) 23.65 (0.931) 19.90 (0.783) Value mm (in.) Max. 3.4 (0.134) 0.25 (0.010) 0.50 (0.020) 18.15 (0.715) 14.10 (0.555) 24.15 (0.951) 20.10 (0.791) 1.0 (0.039) 0.1 (0.004) 1.15 (0.045) 17
PRELIMINARY
82093AA (IOAPIC)
6.0.
TESTABILITY
The purpose of this section is to explain the test modes that the Stand Alone IOAPIC device will support. There are four test modes available in this device. 1. Tri-state all the outputs 2. Drive 1's to the outputs 3. Drive 0's to the outputs 4. Nand Tree The Nand Tree and Tri-state mode are also valuable to the board testing environment. The Nand Tree can identify opens and shorts on input and output pins and the Tri-State mode can give the ATE tester control over other devices in the system. The test modes are decoded from the INTIN inputs (INTIN21:17) qualified with the TESTIN# pin. Test mode selection is asynchronous. The following test modes are used: Table 5. IOAPIC Test Modes Test Modes NAND Tree Tristate All Outputs Drive Outputs High Drive Outputs Low Drive Outputs Low INTIN 21:17 x1xxx xxx1x 00000 00101 00100 00100
6.1.
Tri-State Of All Output Pins
This mode is useful during ATE testing at a board level. If the IOAPIC tri-states its outputs, the tester can drive the signals without having to overdrive the IOAPIC output buffers. This mode is enabled in two ways: 1. Asserting the RESET pin. During RESET, all the IOAPIC device outputs are Tri-State 2. TESTIN# = 0 and INTIN(21:17) = 00000
6.2.
Drive 1's to all the output pins
This is a special test mode that enables all the outputs are driving logic ones. How to enable this mode: 1. TESTIN# = 0 2. INTIN(21:17) = 00101 3. All the outputs will be driven to 1
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PRELIMINARY
82093AA (IOAPIC)
6.3.
Drive 0's to all the output pins
This is a special test mode that enables all the outputs into a low state. How to enable this mode: 1. TESTIN# = 0 2. INTIN(21:17) = 00100 3. All the outputs will be driven to 0
6.4.
NAND Tree
The NAND tree is also useful for Automated Test Equipment (ATE) at board level testing. The NAND Tree allows the tester to test the solder connections for each individual signal pin. How to enable this mode: 1. All pins included in the NAND tree are driven to 1 2. TESTIN# = 0 3. INTIN(21:17) = x1x1x Table 6. NAND Tree Signal Name DATA_2 DATA_1 DATA_0 CSb APICD_0 APICD_1 SMIOUTb APICACK2b APICREQb APICACKb WRb RDb SA_0 SA_1 DIb INTIN_13 INTIN_0 INTIN_14 INTIN_15 Pin# 57 58 59 61 4 5 6 8 9 10 11 12 13 14 15 16 17 18 21 Comment Start Nandtree Nand tree Order 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 19
PRELIMINARY
82093AA (IOAPIC)
Table 6. NAND Tree Signal Name INTIN_12 INTIN_11 INTIN_10 INTIN_3 INTIN_4 INTIN_5 INTIN_6 INTIN_7 INTIN_9 INTIN_8 INTIN_1 INTIN_2 INTIN_16 INTIN_17 INTIN_18 INTIN_19 INTIN_20 INTIN_21 INTIN_22 INTIN_23 DATA_7 DATA_6 DATA_5 DATA_4 DATA_3 Pin# 22 23 24 25 26 27 28 29 30 31 34 35 37 38 39 40 41 42 43 44 50 53 54 55 56 Nand tree Output Comment Nand tree Order 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Output
20
PRELIMINARY

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